Addresses the Challenges Associated with System-on-Chip Integration

Network-on-Chip: The Next Generation of System-on-Chip Integration

Utilizing examples of chips that have been implemented in industry and academia, this text presents the full architectural design of components verified through implementation in industrial CAD tools. It describes NoC research and developments, incorporates theoretical proofs strengthening the analysis procedures, and includes algorithms used in NoC design and synthesis. In addition, it considers other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.

This text comprises 12 chapters and covers:

• The evolution of NoC from SoC—its research and developmental challenges
• NoC protocols, elaborating flow control, available network topologies, routing mechanisms, fault tolerance, quality-of-service support, and the design of network interfaces
• The router design strategies followed in NoCs
• The evaluation mechanism of NoC architectures
• The application mapping strategies followed in NoCs
• Low-power design techniques specifically followed in NoCs
• The signal integrity and reliability issues of NoC
• The details of NoC testing strategies reported so far
• The problem of synthesizing application-specific NoCs
• Reconfigurable NoC design issues
• Direction of future research and development in the field of NoC

Network-on-Chip: The Next Generation of System-on-Chip Integration